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ICCAD
2005
IEEE
106views Hardware» more  ICCAD 2005»
15 years 9 months ago
New decompilation techniques for binary-level co-processor generation
—Existing ASIPs (application-specific instruction-set processors) and compiler-based co-processor synthesis approaches meet the increasing performance requirements of embedded ap...
Greg Stiff, Frank Vahid
ICCAD
2001
IEEE
217views Hardware» more  ICCAD 2001»
15 years 9 months ago
ASF: A Practical Simulation-Based Methodology for the Synthesis of Custom Analog Circuits
: This paper describes ASF, a novel cell-level analog synthesis framework that can size and bias a given circuit topology subject to a set of performance objectives and a manufactu...
Michael Krasnicki, Rodney Phelps, James R. Hellums...
102
Voted
CVPR
2010
IEEE
15 years 9 months ago
Single Image Depth Estimation From Predicted Semantic Labels
We consider the problem of estimating the depth of each pixel in a scene from a single monocular image. Unlike traditional approaches [18, 19], which attempt to map from appearanc...
Beyang Liu, Stephen Gould, Daphne Koller
87
Voted
CVPR
2010
IEEE
15 years 9 months ago
Face Recognition with Learning-based Descriptor
We present a novel approach to address the representation issue and the matching issue in face recognition (verification). Firstly, our approach encodes the micro-structures of t...
Zhimin Cao, Qi Yin, Jian Sun, Xiaoou Tang
VMCAI
2010
Springer
15 years 7 months ago
Regular Linear Temporal Logic with Past
This paper upgrades Regular Linear Temporal Logic (RLTL) with past operators and complementation. RLTL is a temporal logic that extends the expressive power of linear temporal logi...
César Sánchez, Martin Leucker