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» Analog Circuit Modeling in SystemC
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GLVLSI
2002
IEEE
108views VLSI» more  GLVLSI 2002»
13 years 11 months ago
Protected IP-core test generation
Design simplification is becoming necessary to respect the target time-to-market of SoCs, and this goal can be obtained by using predesigned IP-cores. However, their correct inte...
Alessandro Fin, Franco Fummi
DAC
2005
ACM
13 years 8 months ago
Timing-driven placement by grid-warping
Grid-warping is a recent placement strategy based on a novel physical analogy: rather than move the gates to optimize their location, it elastically deforms a model of the 2-D chi...
Zhong Xiu, Rob A. Rutenbar
DAC
2003
ACM
13 years 11 months ago
4G terminals: how are we going to design them?
Fourth-generation wireless communication systems (4G) will have totally different requirements than what front-end designers have been coping with up to now. Designs must be targe...
Jan Craninckx, Stéphane Donnay
ISQED
2010
IEEE
128views Hardware» more  ISQED 2010»
13 years 8 months ago
A novel all-digital fractional-N frequency synthesizer architecture with fast acquisition and low spur
Digital implementation of analog function is becoming attractive in CMOS ICs, given the low supply voltage of ultra-scaled process. The conventional fractional-N frequency synthes...
Jun Zhao, Yong-Bin Kim
CSUR
2006
147views more  CSUR 2006»
13 years 6 months ago
A survey of research and practices of Network-on-chip
resents a perspective on existing NoC research. We define the following abstractions: system, network adapter, network, and link to explain and structure the fundamental concepts. ...
Tobias Bjerregaard, Shankar Mahadevan