135 search results - page 17 / 27 » Analog circuit test based on a digital signature |
103
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ISQED
2011
IEEE
14 years 18 days ago
2011
IEEE
—Design optimization methodologies for AMS-SoCs with analog, digital, and mixed-signal portions have not received significant attention, due to their high complexity. In mixed-s...
MJ
2007
14 years 9 months ago
2007
With increasingly smaller feature sizes and higher on-chip densities, the power dissipation of VLSI systems has become a primary concern for designers. This paper first describes...
DPHOTO
2010
14 years 11 months ago
2010
The high level context image analysis regards many fields as face recognition, smile detection, automatic red eye removal, iris recognition, fingerprint verification, etc. Techniq...
88
Voted
MTDT
2003
IEEE
15 years 3 months ago
2003
IEEE
ct Defect-based testing for digital logic concentrates primarily on methods of test application, including for example at-speed structural tests and IDDQ testing. In contrast, defe...
74
Voted
WCE
2007
14 years 11 months ago
2007
—Clock jitter and its effects on signal-to-noise ratio (SNR) were widely investigated in the published literatures. However, most of the issues mainly focused on white-Gaussian-n...