208 search results - page 33 / 42 » Analog circuits optimization based on evolutionary computati... |
ISPD
2010
ACM
15 years 4 months ago
2010
ACM
Double Patterning Lithography (DPL) is one of the few hopeful candidate solutions for the lithography for CMOS process beyond 45nm. DPL assigns the patterns less than a certain di...
KDD
2010
ACM
14 years 8 months ago
2010
ACM
Scalable similarity search is the core of many large scale learning or data mining applications. Recently, many research results demonstrate that one promising approach is creatin...
DAC
2010
ACM
14 years 4 months ago
2010
ACM
This paper presents a logic restructuring technique named node addition and removal (NAR). It works by adding a node into a circuit to replace an existing node and then removing t...
DAC
1999
ACM
15 years 10 months ago
1999
ACM
Recently, several algorithms for interconnect optimization via repeater insertion and wire sizing have appeared based on the Elmore delay model. Using the Devgan noise metric [6] ...
CODES
2004
IEEE
15 years 1 months ago
2004
IEEE
In this paper we present an approach to multi-objective exploration of the mapping space of a mesh-based network-on-chip architecture. Based on evolutionary computing techniques, ...