69 search results - page 11 / 14 » Analog placement with symmetry and other placement constrain... |
ASPDAC
2012
ACM
13 years 5 months ago
2012
ACM
— In this paper, we present an obstacle-aware clock tree synthesis method for through-silicon-via (TSV)-based 3D ICs. A unique aspect of this problem lies in the fact that variou...
GD
2008
Springer
14 years 10 months ago
2008
Springer
Abstract. Constrained graph layout is a recent generalisation of forcedirected graph layout which allows constraints on node placement. We give a constrained graph layout algorithm...
109
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CVPR
2010
IEEE
15 years 6 months ago
2010
IEEE
In this paper, we deal with a generative model for multi-label, interactive segmentation. To estimate the pixel likelihoods for each label, we propose a new higher-order formulatio...
172
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KDD
2012
ACM
13 years 3 days ago
2012
ACM
Display ads on the Internet are often sold in bundles of thousands or millions of impressions over a particular time period, typically weeks or months. Ad serving systems that ass...
DAC
2010
ACM
14 years 10 months ago
2010
ACM
This work proposes a new problem of identifying large and tangled logic structures in a synthesized netlist. Large groups of cells that are highly interconnected to each other can...