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WWW
2007
ACM
16 years 6 months ago
Image annotation by hierarchical mapping of features
In this paper, we propose a novel approach of image annotation by constructing a hierarchical mapping between lowlevel visual features and text features utilizing the relations wi...
Qiankun Zhao, Prasenjit Mitra, C. Lee Giles
VLSID
2002
IEEE
98views VLSI» more  VLSID 2002»
16 years 6 months ago
On Test Scheduling for Core-Based SOCs
We present a mathematical model for the problem of scheduling tests for core-based system-on-chip (SOC) VLSI designs. Given a set of tests for each core in the SOC and a set of te...
Sandeep Koranne
ICCAD
2006
IEEE
101views Hardware» more  ICCAD 2006»
16 years 3 months ago
Guaranteeing performance yield in high-level synthesis
Meeting timing constraint is one of the most important issues for modern design automation tools. This situation is exacerbated with the existence of process variation. Current hi...
Wei-Lun Hung, Xiaoxia Wu, Yuan Xie
ISQED
2009
IEEE
115views Hardware» more  ISQED 2009»
16 years 29 days ago
TuneLogic: Post-silicon tuning of dual-Vdd designs
Modern CMOS manufacturing processes have significant variability, which necessitates guard banding to achieve reasonable yield. It is our thesis that variability should be addres...
Stephen Bijansky, Sae Kyu Lee, Adnan Aziz
172
Voted
GLOBECOM
2009
IEEE
16 years 27 days ago
Impact of Social Networks on Delay Tolerant Routing
Abstract—Delay Tolerant Networks (DTNs) are wireless networks in which at any given time instance, the probability of having a complete path from a source to destination is low d...
Eyuphan Bulut, Zijian Wang, Boleslaw K. Szymanski
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