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ASPDAC
2007
ACM
152views Hardware» more  ASPDAC 2007»
15 years 9 months ago
A Graph Reduction Approach to Symbolic Circuit Analysis
A new graph reduction approach to symbolic circuit analysis is developed in this paper. A Binary Decision Diagram (BDD) mechanism is formulated, together with a specially designed ...
Guoyong Shi, Weiwei Chen, C.-J. Richard Shi
ER
2000
Springer
126views Database» more  ER 2000»
15 years 8 months ago
Tool Support for Reuse of Analysis Patterns - A Case Study
: The size and complexity of modern information systems together with requirements for short development time increase the demands for reuse of already existing solutions. The idea...
Petia Wohed
SAC
2011
ACM
14 years 8 months ago
Fault tolerance evaluation and schedulability analysis
The use of real-time systems can differ from their initial design and requirements. New missions may take place in a more agressive environment and cause faults that are not manag...
Florian Many, David Doose
ISSS
1995
IEEE
161views Hardware» more  ISSS 1995»
15 years 8 months ago
Synthesis of pipelined DSP accelerators with dynamic scheduling
To construct complete systems on silicon, application speci c DSP accelerators are needed to speed up the execution of high throughput DSP algorithms. In this paper, a methodology...
Patrick Schaumont, Bart Vanthournout, Ivo Bolsens,...
ICASSP
2008
IEEE
15 years 11 months ago
Filter bank design based on minimization of individual aliasing terms for minimum mutual information subband adaptive beamformin
This paper presents new filter bank design methods for subband adaptive beamforming. In this work, we design analysis and synthesis prototypes for modulated filter banks so as t...
Ken'ichi Kumatani, John W. McDonough, S. Schachl, ...