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» Analysis of Heuristic Synergies
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JSAC
2010
194views more  JSAC 2010»
14 years 12 months ago
Burst communication by means of buffer allocation in body sensor networks: Exploiting signal processing to reduce the number of
Abstract—Monitoring human movements using wireless sensory devices promises to revolutionize the delivery of healthcare services. Such platforms use inertial information of their...
Hassan Ghasemzadeh, Vitali Loseu, Sarah Ostadabbas...
ICCD
2001
IEEE
119views Hardware» more  ICCD 2001»
15 years 10 months ago
A Functional Validation Technique: Biased-Random Simulation Guided by Observability-Based Coverage
We present a simulation-based semi-formal verification method for sequential circuits described at the registertransfer level. The method consists of an iterative loop where cove...
Serdar Tasiran, Farzan Fallah, David G. Chinnery, ...
CC
2006
Springer
182views System Software» more  CC 2006»
15 years 5 months ago
Selective Runtime Memory Disambiguation in a Dynamic Binary Translator
Abstract. Alias analysis, traditionally performed statically, is unsuited for a dynamic binary translator (DBT) due to incomplete control-flow information and the high complexity o...
Bolei Guo, Youfeng Wu, Cheng Wang, Matthew J. Brid...
CLEF
2009
Springer
15 years 2 months ago
UNIBA-SENSE @ CLEF 2009: Robust WSD Task
This paper presents the participation of the semantic N-levels search engine SENSE at the CLEF 2009 Ad Hoc Robust-WSD Task. During the participation at the same task of CLEF 2008,...
Pierpaolo Basile, Annalina Caputo, Giovanni Semera...
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CODES
2006
IEEE
15 years 7 months ago
Data reuse driven energy-aware MPSoC co-synthesis of memory and communication architecture for streaming applications
The memory subsystem of a complex multiprocessor systemson-chip (MPSoC) is an important contributor to the chip power consumption. The selection of memory architecture, as well as...
Ilya Issenin, Nikil Dutt