291 search results - page 19 / 59 » Analysis of a reconfigurable network processor |
128
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FPGA
2010
ACM
14 years 12 months ago
2010
ACM
We use reconfigurable hardware to construct a high throughput Bayesian computing machine (BCM) capable of evaluating probabilistic networks with arbitrary DAG (directed acyclic gr...
118
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EH
2004
IEEE
15 years 3 months ago
2004
IEEE
This work deals with the design of analog circuits for Artificial Neural Networks (ANNs) controllers using an Evolvable Hardware (EHW) platform. ANNs are massively parallel system...
NCA
2005
IEEE
15 years 5 months ago
2005
IEEE
In this paper, fundamental conditions which bound the network processing unit (NPU) worst-case performance are established. In particular, these conditions formalize and integrate...
109
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IPPS
2006
IEEE
15 years 5 months ago
2006
IEEE
Modern network processors support high levels of parallelism in packet processing by supporting multiple threads that execute on a micro-engine. Threads switch context upon encoun...
IPPS
2005
IEEE
15 years 5 months ago
2005
IEEE
As semiconductor feature sizes decrease, interconnect delay is becoming a dominant component of processor cycle times. This creates a critical need to shift microarchitectural des...