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» Analysis of a reconfigurable network processor
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FPGA
2008
ACM
151views FPGA» more  FPGA 2008»
15 years 1 months ago
Beyond the arithmetic constraint: depth-optimal mapping of logic chains in LUT-based FPGAs
Look-up table based FPGAs have migrated from a niche technology for design prototyping to a valuable end-product component and, in some cases, a replacement for general purpose pr...
Michael T. Frederick, Arun K. Somani
MICRO
2010
IEEE
167views Hardware» more  MICRO 2010»
14 years 9 months ago
Erasing Core Boundaries for Robust and Configurable Performance
Single-thread performance, reliability and power efficiency are critical design challenges of future multicore systems. Although point solutions have been proposed to address thes...
Shantanu Gupta, Shuguang Feng, Amin Ansari, Scott ...
AINA
2006
IEEE
15 years 1 months ago
DiVES: A Distributed Support for Networked Virtual Environments
This paper presents DiV ES, a distributed support for the development of networked Distributed Virtual Environments. DiV ES exploits the publish subscribe interaction model to def...
A. Bonotti, Luca Genovali, Laura Ricci
CASES
2006
ACM
15 years 5 months ago
High-level power analysis for multi-core chips
Technology trends have led to the advent of multi-core chips in the form of both general-purpose chip multiprocessors (CMPs) and embedded multi-processor systems-on-a-chip (MPSoCs...
Noel Eisley, Vassos Soteriou, Li-Shiuan Peh
ISCA
2005
IEEE
121views Hardware» more  ISCA 2005»
15 years 5 months ago
Direct Cache Access for High Bandwidth Network I/O
Recent I/O technologies such as PCI-Express and 10Gb Ethernet enable unprecedented levels of I/O bandwidths in mainstream platforms. However, in traditional architectures, memory ...
Ram Huggahalli, Ravi R. Iyer, Scott Tetrick