291 search results - page 36 / 59 » Analysis of a reconfigurable network processor |
100
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SC
2004
ACM
15 years 5 months ago
2004
ACM
This paper is structured as follows. Section 2 gives an architectural description of BlueGene/L. Section 3 analyzes the issue of “computational noise” – the effect that the o...
91
Voted
AINA
2007
IEEE
15 years 6 months ago
2007
IEEE
Continuous improvements in integration scale have made major microprocessor vendors to move to designs that integrate several processor cores on the same chip. Chip-multiprocessor...
MSS
1999
IEEE
15 years 4 months ago
1999
IEEE
The High Performance Storage System (HPSS) is currently deployed on the open and secure networks at Los Alamos National Laboratory (LANL). Users of the Accelerated Strategic Compu...
SIGCOMM
1996
ACM
15 years 3 months ago
1996
ACM
This paper describes several techniques designed to improve protocol latency, and reports on their effectiveness when measured on a modern RISC machine employing the DEC Alpha pro...
113
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ISCA
2008
IEEE
15 years 6 months ago
2008
IEEE
As the number of cores per die increases, be they processors, memory blocks, or custom accelerators, the on-chip interconnect the cores use to communicate gains importance. We beg...