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CASES
2001
ACM
15 years 3 months ago
Heads and tails: a variable-length instruction format supporting parallel fetch and decode
Abstract. Existing variable-length instruction formats provide higher code densities than fixed-length formats, but are ill-suited to pipelined or parallel instruction fetch and de...
Heidi Pan, Krste Asanovic
EUROPAR
1997
Springer
15 years 3 months ago
Modulo Scheduling with Cache Reuse Information
Instruction scheduling in general, and software pipelining in particular face the di cult task of scheduling operations in the presence of uncertain latencies. The largest contrib...
Chen Ding, Steve Carr, Philip H. Sweany
RTCSA
2003
IEEE
15 years 4 months ago
Deterministic and Statistical Deadline Guarantees for a Mixed Set of Periodic and Aperiodic Tasks
Current hard real-time technologies are unable to support a new class of applications that have real-time constraints but with dynamic request arrivals and unpredictable resource r...
Minsoo Ryu, Seongsoo Hong
ICCD
2006
IEEE
115views Hardware» more  ICCD 2006»
15 years 8 months ago
Microarchitecture and Performance Analysis of Godson-2 SMT Processor
—This paper introduces the microarchitecture and logical implementation of SMT (Simultaneous Multithreading) improvement of Godson-2 processor which is a 64-bit, four-issue, out-...
Zusong Li, Xianchao Xu, Weiwu Hu, Zhimin Tang
ESTIMEDIA
2006
Springer
15 years 3 months ago
Loop Nest Splitting for WCET-Optimization and Predictability Improvement
This paper presents the influence of the loop nest splitting source code optimization on the worst-case execution time (WCET). Loop nest splitting minimizes the number of executed...
Heiko Falk, Martin Schwarzer