Sciweavers

93 search results - page 11 / 19
» Analysis of checksum-based execution schemes for pipelined p...
Sort
View
94
Voted
ICS
1999
Tsinghua U.
15 years 3 months ago
Classifying load and store instructions for memory renaming
Memory operations remain a significant bottleneck in dynamically scheduled pipelined processors, due in part to the inability to statically determine the existence of memory addr...
Glenn Reinman, Brad Calder, Dean M. Tullsen, Gary ...
112
Voted
ISCA
1991
IEEE
162views Hardware» more  ISCA 1991»
15 years 3 months ago
Comparison of Hardware and Software Cache Coherence Schemes
We use mean value analysis models to compare representative hardware and software cache coherence schemes for a large-scale shared-memory system. Our goal is to identify the workl...
Sarita V. Adve, Vikram S. Adve, Mark D. Hill, Mary...
RTAS
1996
IEEE
15 years 3 months ago
Efficient worst case timing analysis of data caching
Recent progress in worst case timing analysis of programs has made it possible to perform accurate timing analysis of pipelined execution and instruction caching, which is necessa...
Sung-Kwan Kim, Sang Lyul Min, Rhan Ha
LREC
2008
137views Education» more  LREC 2008»
15 years 1 months ago
The TextPro Tool Suite
We present TextPro, a suite of modular Natural Language Processing (NLP) tools for analysis of Italian and English texts. The suite has been designed so as to integrate and reuse ...
Emanuele Pianta, Christian Girardi, Roberto Zanoli
112
Voted
LCN
2005
IEEE
15 years 5 months ago
Implementation and Performance Analysis of a Packet Scheduler on a Programmable Network Processor
— The problem of achieving fairness in the allocation of the bandwidth resource on a link shared by multiple flows of traffic has been extensively researched over the last deca...
Fariza Sabrina, Salil S. Kanhere, Sanjay Jha