93 search results - page 13 / 19 » Analysis of checksum-based execution schemes for pipelined p... |
ISLPED
1999
ACM
15 years 4 months ago
1999
ACM
In this paper, we propose a technique that uses an additional mini cache, the L0-Cache, located between the instruction cache I-Cache and the CPU core. This mechanism can provid...
94
Voted
EDBT
2006
ACM
15 years 11 months ago
2006
ACM
Skyline queries help users make intelligent decisions over complex data, where different and often conflicting criteria are considered. Current skyline computation methods are rest...
DSN
2006
IEEE
15 years 5 months ago
2006
IEEE
Protecting the register value and its data buses is crucial to reliable computing in high-performance microprocessors due to the increasing susceptibility of CMOS circuitry to sof...
SIROCCO
2000
15 years 1 months ago
2000
ABSTRACT: This work considers the problem of performing a set of N tasks on a set of P cooperating message-passing processors (P N). The processors use a group communication servi...
DATE
2007
IEEE
15 years 6 months ago
2007
IEEE
Recently there has been considerable interest in incorporating timing effects of microarchitectural features of processors (e.g. caches and pipelines) into the schedulability anal...