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DSN
2009
IEEE
15 years 6 months ago
2009
IEEE
The threat of soft error induced system failure in high performance computing systems has become more prominent, as we adopt ultra-deep submicron process technologies. In this pap...
ISCA
2007
IEEE
15 years 5 months ago
2007
IEEE
The negative performance impact of branch mis-predictions can be reduced by exploiting control independence (CI). When a branch mis-predicts, the wrong-path instructions up to the...
ICS
2004
Tsinghua U.
15 years 5 months ago
2004
Tsinghua U.
With processor speeds continuing to outpace the memory subsystem, cache missing memory operations continue to become increasingly important to application performance. In response...
FPL
2007
Springer
15 years 5 months ago
2007
Springer
In this paper, we propose a first step towards a time predictable computer architecture for single-chip multiprocessing (CMP). CMP is the actual trend in server and desktop syste...
ISCA
2003
IEEE
15 years 4 months ago
2003
IEEE
In a single second a modern processor can execute billions of instructions. Obtaining a bird’s eye view of the behavior of a program at these speeds can be a difficult task whe...