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IPPS
1998
IEEE
15 years 3 months ago
Parallel Performance Visualization Using Moments of Utilization Data
We propose a new parallel performance visualization scheme, based on a simple moment analysis of processor utilization data. This method combines the scalability advantages of sta...
T. J. Godin, Michael J. Quinn, Cherri M. Pancake
ASPDAC
2004
ACM
75views Hardware» more  ASPDAC 2004»
15 years 5 months ago
Power-performance trade-off using pipeline delays
— We study the delays faced by instructions in the pipeline of a superscalar processor and its impact on power and performance. Instructions that are ready-on-dispatch (ROD) are ...
G. Surendra, Subhasis Banerjee, S. K. Nandy
RTSS
2003
IEEE
15 years 4 months ago
Experimental Evaluation of Code Properties for WCET Analysis
This paper presents a quantification of the timing effects that advanced processor features like data and instruction cache, pipelines, branch prediction units and out-oforder ex...
Antoine Colin, Stefan M. Petters
DSN
2007
IEEE
15 years 3 months ago
Augmenting Branch Predictor to Secure Program Execution
Although there are various ways to exploit software vulnerabilities for malicious attacks, the attacks always result in unexpected behavior in program execution, deviating from wh...
Yixin Shi, Gyungho Lee
ISCA
2005
IEEE
126views Hardware» more  ISCA 2005»
15 years 5 months ago
A Tree Based Router Search Engine Architecture with Single Port Memories
Pipelined forwarding engines are used in core routers to meet speed demands. Tree-based searches are pipelined across a number of stages to achieve high throughput, but this resul...
Florin Baboescu, Dean M. Tullsen, Grigore Rosu, Su...