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» Analysis of power consumption in VLSI global interconnects
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ASPDAC
2009
ACM
145views Hardware» more  ASPDAC 2009»
15 years 4 months ago
High performance on-chip differential signaling using passive compensation for global communication
— To address the performance limitation brought by the scaling issues of on-chip global wires, a new configuration for global wiring using on-chip lossy transmission lines is pr...
Ling Zhang, Yulei Zhang, Akira Tsuchiya, Masanori ...
JCM
2008
70views more  JCM 2008»
14 years 9 months ago
Reed-Solomon Codes for Low Power Communications
Power consumption is a critical issue for many applications running on autonomous battery operated devices. In the context of low power communications, the use of Forward Error Cor...
Lionel Biard, Dominique Noguet
ISVLSI
2008
IEEE
104views VLSI» more  ISVLSI 2008»
15 years 4 months ago
Thermal-Aware Placement of Standard Cells and Gate Arrays: Studies and Observations
In high-performance VLSI circuits, the on-chip power densities are playing dominant role due to increased scaling of technology, increasing number of components, frequency and ban...
Prasun Ghosal, Tuhina Samanta, Hafizur Rahaman, Pa...
ISVLSI
2006
IEEE
114views VLSI» more  ISVLSI 2006»
15 years 3 months ago
A Low Power Lookup Technique for Multi-Hashing Network Applications
Many network security applications require large virus signature sets to be maintained, retrieved, and compared against the network streams. Software applications frequently fail ...
Ilhan Kaya, Taskin Koçak
GLVLSI
2005
IEEE
122views VLSI» more  GLVLSI 2005»
15 years 3 months ago
Thermal aware cell-based full-chip electromigration reliability analysis
A hierarchical scheme with cells and modules is crucial for managing design complexity during a large integrated circuit design. We present a methodology for thermal aware cell-ba...
Syed M. Alam, Donald E. Troxel, Carl V. Thompson