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» Analysis of power consumption in VLSI global interconnects
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VLSID
2007
IEEE
104views VLSI» more  VLSID 2007»
15 years 10 months ago
Customization of Register File Banking Architecture for Low Power
Register file banking is an effective alternative to monolithic register files in embedded processor based systems. In this work, we propose techniques for performing application s...
Rakesh Nalluri, Rohan Garg, Preeti Ranjan Panda
83
Voted
ICCD
2008
IEEE
175views Hardware» more  ICCD 2008»
15 years 6 months ago
On-chip high performance signaling using passive compensation
— To address the performance limitation brought by the scaling issues of on-chip global wires, a new configuration for global wiring using on-chip lossy transmission lines(T-lin...
Yulei Zhang, Ling Zhang, Akira Tsuchiya, Masanori ...
DSD
2002
IEEE
96views Hardware» more  DSD 2002»
15 years 2 months ago
Networks on Silicon: Blessing or Nightmare?
Continuing VLSI technology scaling raises several deep submicron (DSM) problems like relatively slow interconnect, power dissipation and distribution, and signal integrity. Those ...
Paul Wielage, Kees G. W. Goossens
ASAP
2006
IEEE
110views Hardware» more  ASAP 2006»
15 years 3 months ago
Loop Transformation Methodologies for Array-Oriented Memory Management
Abstract – The storage requirements in data-dominant signal processing systems, whose behavior is described by arraybased, loop-organized algorithmic specifications, have an imp...
Florin Balasa, Per Gunnar Kjeldsberg, Martin Palko...
ICCAD
2004
IEEE
95views Hardware» more  ICCAD 2004»
15 years 6 months ago
Low-power programmable routing circuitry for FPGAs
We propose two new FPGA routing switch designs that are programmable to operate in three different modes: highspeed, low-power or sleep. High-speed mode provides similar power an...
Jason Helge Anderson, Farid N. Najm