111 search results - page 18 / 23 » Analysis of power consumption in VLSI global interconnects |
TC
2008
14 years 9 months ago
2008
The design and performance of next-generation chip multiprocessors (CMPs) will be bound by the limited amount of power that can be dissipated on a single die. We present photonic n...
ICCAD
2002
IEEE
15 years 6 months ago
2002
IEEE
As the scale of system integration continues to grow, the on-chip communication becomes the ultimate bottleneck of system performance and the primary determinant of system archite...
ISVLSI
2007
IEEE
15 years 3 months ago
2007
IEEE
In this paper, the problem of sizing MOS Current Mode Logic (MCML) circuits is addressed. The Pareto front is introduced as a useful analysis tool to explore the design space of e...
VLSID
2006
IEEE
15 years 3 months ago
2006
IEEE
Low density parity check (LDPC) codes are one of the most powerful error correcting codes known. Recent research have pointed out their potential for a low cost, low latency hardw...
SLIP
2005
ACM
15 years 3 months ago
2005
ACM
Routability optimization has become a major concern in the physical design cycle of VLSI circuits. Due to the recent advances in VLSI technology, interconnect has become a dominan...