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» Analysis of power consumption in VLSI global interconnects
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GLVLSI
2003
IEEE
171views VLSI» more  GLVLSI 2003»
15 years 2 months ago
Combining wire swapping and spacing for low-power deep-submicron buses
We propose an approach for reducing the energy consumption of address buses that targets both the switching and the crosstalk components of power dissipation. The method is based ...
Enrico Macii, Massimo Poncino, Sabino Salerno
DATE
2010
IEEE
121views Hardware» more  DATE 2010»
15 years 2 months ago
Properties of and improvements to time-domain dynamic thermal analysis algorithms
—Temperature has a strong influence on integrated circuit (IC) performance, power consumption, and reliability. However, accurate thermal analysis can impose high computation co...
Xi Chen, Robert P. Dick, Li Shang
ISVLSI
2003
IEEE
91views VLSI» more  ISVLSI 2003»
15 years 2 months ago
Three-Dimensional Integrated Circuits: Performance, Design Methodology, and CAD Tools
Three-dimensional integration technologies have been proposed in order to mitigate design challenges posed by deep-submicron interconnect. By providing multiple layers of active d...
Shamik Das, Anantha Chandrakasan, Rafael Reif
VLSID
2004
IEEE
107views VLSI» more  VLSID 2004»
15 years 10 months ago
Performance Analysis of Inter Cluster Communication Methods in VLIW Architecture
With increasing demands for high performance by embedded systems, especially by digital signal processing applications, embedded processors must increase available instruction lev...
Sourabh Saluja, Anshul Kumar
78
Voted
GLVLSI
2006
IEEE
152views VLSI» more  GLVLSI 2006»
15 years 3 months ago
2 Gbps SerDes design based on IBM Cu-11 (130nm) standard cell technology
This paper introduces a standard cell based design for a Serializer and Deserializer (SerDes) communication link. The proposed design is area, power and design time efficient as c...
Rashed Zafar Bhatti, Monty Denneau, Jeff Draper