111 search results - page 21 / 23 » Analysis of power consumption in VLSI global interconnects |
MICRO
2003
IEEE
15 years 2 months ago
2003
IEEE
It is widely accepted that the disproportionate scaling of transistor and conventional on-chip interconnect performance presents a major barrier to future high performance systems...
TVLSI
1998
14 years 9 months ago
1998
—In most low-power VLSI designs, the supply voltage is usually reduced to lower the total power consumption. However, the device speed will be degraded as the supply voltage goes...
75
Voted
DATE
2004
IEEE
15 years 1 months ago
2004
IEEE
Latency-insensitive systems were recently proposed by Carloni et al. as a correct-by-construction methodology for single-clock system-on-a-chip (SoC) design using predesigned IP b...
71
Voted
DAC
2006
ACM
15 years 10 months ago
2006
ACM
Three-dimensional (3-D) integrated circuits have emerged as promising candidates to overcome the interconnect bottlenecks of nanometer scale designs. While they offer several othe...
ICCAD
2006
IEEE
15 years 6 months ago
2006
IEEE
Process variations in modern VLSI technologies are growing in both magnitude and dimensionality. To assess performance variability, complex simulation and performance models param...