111 search results - page 7 / 23 » Analysis of power consumption in VLSI global interconnects |
GLVLSI
2007
IEEE
15 years 4 months ago
2007
IEEE
We propose an interconnect reorganization algorithm for reduction stages in parallel multipliers. It aims at minimizing power consumption for given static probabilities at the pri...
ICCAD
2003
IEEE
15 years 6 months ago
2003
IEEE
— In this paper, we present a high-level power model to estimate the power consumption in semi-global and global interconnects. Such interconnects are used for communications bet...
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Voted
VLSID
2002
IEEE
15 years 10 months ago
2002
IEEE
Interconnection networks in Systems-On-Chip begin to have a non-negligible impact on the power consumption of a whole system. This is because of increasing inter-wire capacitances...
ICCAD
2002
IEEE
15 years 6 months ago
2002
IEEE
As the VLSI technology scaling down, the electromigration problem becomes one of the major concerns in high-performance IC design for both power network and signal interconnects. ...
ICCAD
2000
IEEE
15 years 2 months ago
2000
IEEE
Coupling effects between on-chip interconnects must be addressed in ultra deep submicron VLSI and system-on-a-chip (SoC) designs. A new low-power bus encoding scheme is proposed t...