111 search results - page 8 / 23 » Analysis of power consumption in VLSI global interconnects |
ISLPED
2003
ACM
15 years 2 months ago
2003
ACM
Ever shrinking device sizes and innovative micro-architectural and circuit design techniques have made it possible to have multi-million transistor systems running at multi-gigahe...
DAC
1999
ACM
15 years 1 months ago
1999
ACM
In deep submicron technology, IR-drop and clock skew issues become more crucial to the functionality of chip. This paper presents a oorplan-based power and clock distribution meth...
DAC
2005
ACM
15 years 10 months ago
2005
ACM
Achieving design closure is one of the biggest headaches for modern VLSI designers. This problem is exacerbated by high-level design automation tools that ignore increasingly impo...
103
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ISLPED
2010
ACM
14 years 9 months ago
2010
ACM
This paper proposes a framework for (signal) interconnect power optimization at the global routing stage. In a typical design flow, the primary objective of global routing is mini...
106
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AC
2005
Springer
14 years 9 months ago
2005
Springer
Reducing power consumption has become a major challenge in the design and operation of today's computer systems. This chapter describes different techniques addressing this c...