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95
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VALUETOOLS
2006
ACM
167views Hardware» more  VALUETOOLS 2006»
15 years 4 months ago
Detailed cache simulation for detecting bottleneck, miss reason and optimization potentialities
Cache locality optimization is an efficient way for reducing the idle time of modern processors in waiting for needed data. This kind of optimization can be achieved either on the...
Jie Tao, Wolfgang Karl
IWMMDBMS
1998
91views more  IWMMDBMS 1998»
14 years 11 months ago
Q-L/MRP: A Buffer Management Mechanism for QoS Support in a Multimedia DBMS
Multimedia database systems (MMDBSs) have to be capable to handle efficiently time-dependent and timeindependent data, and to support Quality-of-Service (QoS). To support continuo...
Pål Halvorsen, Vera Goebel, Thomas Plagemann
PCI
2005
Springer
15 years 4 months ago
Tuning Blocked Array Layouts to Exploit Memory Hierarchy in SMT Architectures
Cache misses form a major bottleneck for memory-intensive applications, due to the significant latency of main memory accesses. Loop tiling, in conjunction with other program tran...
Evangelia Athanasaki, Kornilios Kourtis, Nikos Ana...
104
Voted
MICRO
2003
IEEE
152views Hardware» more  MICRO 2003»
15 years 3 months ago
A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor
Single-event upsets from particle strikes have become a key challenge in microprocessor design. Techniques to deal with these transient faults exist, but come at a cost. Designers...
Shubhendu S. Mukherjee, Christopher T. Weaver, Joe...
ISPAN
2000
IEEE
15 years 2 months ago
Versatile Processor Design for Efficiency and High Performance
We present new architectural concepts for uniprocessor designs that conform to the data-driven computation paradigm. Usage of our D2 -CPU (Data-Driven processor) follows the natura...
Sotirios G. Ziavras