2036 search results - page 323 / 408 » Analysis of the XC6000 Architecture for Embedded System Desi... |
72
Voted
ISLPED
2005
ACM
15 years 3 months ago
2005
ACM
Tuning a configurable cache subsystem to an application can greatly reduce memory hierarchy energy consumption. Previous tuning methods use a level one configurable cache only, or...
75
Voted
SAMOS
2004
Springer
15 years 3 months ago
2004
Springer
— Architectural resources and program recurrences are the main limitations to the amount of Instruction-Level Parallelism (ILP) exploitable from loops, the most time-consuming pa...
161
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ICCAD
2003
IEEE
15 years 3 months ago
2003
IEEE
While performance, area, and power constraints have been the driving force in designing current communication-enabled embedded systems, post-fabrication and run-time adaptability ...
GLVLSI
1998
IEEE
15 years 2 months ago
1998
IEEE
With the increased clock frequency of modern, high-performance processors over 500 MHz, in some cases, limiting the power dissipation has become the most stringent design target. ...
DAC
2009
ACM
15 years 11 months ago
2009
ACM
State-of-the-art integral-equation-based solvers rely on techniques that can perform a matrix-vector multiplication in O(N) complexity. In this work, a fast inverse of linear comp...