Sciweavers

98 search results - page 12 / 20
» Analytic Evaluation of Shared-memory Systems with ILP Proces...
Sort
View
HIPC
2005
Springer
15 years 2 months ago
Preemption Adaptivity in Time-Published Queue-Based Spin Locks
Abstract. The proliferation of multiprocessor servers and multithreaded applications has increased the demand for high-performance synchronization. Traditional scheduler-based lock...
Bijun He, William N. Scherer III, Michael L. Scott
SC
1995
ACM
15 years 29 days ago
Lazy Release Consistency for Hardware-Coherent Multiprocessors
Release consistency is a widely accepted memory model for distributed shared memory systems. Eager release consistency represents the state of the art in release consistent protoc...
Leonidas I. Kontothanassis, Michael L. Scott, Rica...
66
Voted
IPPS
1997
IEEE
15 years 1 months ago
Performance Comparison of Processor Scheduling Strategies in a Distributed-Memory Multicomputer System
Abstract — Processor scheduling has received considerable attention in the context of shared-memory multiprocessor systems but has not received as much attention in distributed-m...
Yuet-Ning Chan, Sivarama P. Dandamudi, Shikharesh ...
CODES
2004
IEEE
15 years 1 months ago
A loop accelerator for low power embedded VLIW processors
The high transistor density afforded by modern VLSI processes have enabled the design of embedded processors that use clustered execution units to deliver high levels of performan...
Binu K. Mathew, Al Davis
TPDS
2010
144views more  TPDS 2010»
14 years 7 months ago
Performance Evaluation of Dynamic Speculative Multithreading with the Cascadia Architecture
—Thread-level parallelism (TLP) has been extensively studied in order to overcome the limitations of exploiting instruction-level parallelism (ILP) on high-performance superscala...
David A. Zier, Ben Lee