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» Analytical Design of Evolutionary Control Flow Components
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ISSS
1999
IEEE
151views Hardware» more  ISSS 1999»
15 years 2 months ago
Optimized System Synthesis of Complex RT Level Building Blocks from Multirate Dataflow Graphs
In order to cope with the ever increasing complexity of todays application specific integrated circuits, a building block based design methodology is established. The system is co...
Jens Horstmannshoff, Heinrich Meyr
HYBRID
2010
Springer
15 years 5 months ago
On a control algorithm for time-varying processor availability
We consider an anytime control algorithm for the situation when the processor resource availability is time-varying. The basic idea is to calculate the components of the control i...
Vijay Gupta
CODES
2007
IEEE
15 years 4 months ago
Predator: a predictable SDRAM memory controller
Memory requirements of intellectual property components (IP) in contemporary multi-processor systems-on-chip are increasing. Large high-speed external memories, such as DDR2 SDRAM...
Benny Akesson, Kees Goossens, Markus Ringhofer
ICS
2009
Tsinghua U.
15 years 2 months ago
A comprehensive power-performance model for NoCs with multi-flit channel buffers
Large Multi-Processor Systems-on-Chip use Networks-on-Chip with a high degree of reusability and scalability for message communication. Therefore, network infrastructure is a cruc...
Mohammad Arjomand, Hamid Sarbazi-Azad
DATE
2010
IEEE
156views Hardware» more  DATE 2010»
15 years 3 months ago
Domain specific architecture for next generation wireless communication
—In order to solve the challenges in processor design for the next generation wireless communication systems, this paper first proposes a system level design flow for communicati...
Botao Zhang, Hengzhu Liu, Heng Zhao, Fangzheng Mo,...