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» Analytical Modeling of Pipeline Parallelism
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SAMOS
2004
Springer
15 years 2 months ago
Scalable Instruction-Level Parallelism.
This paper presents a model for instruction-level distributed computing that allows the implementation of scalable chip multiprocessors. Based on explicit microthreading it serves ...
Chris R. Jesshope
90
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IPPS
2006
IEEE
15 years 3 months ago
Design flow for optimizing performance in processor systems with on-chip coarse-grain reconfigurable logic
A design flow for processor platforms with on-chip coarse-grain reconfigurable logic is presented. The reconfigurable logic is realized by a 2-Dimensional Array of Processing Elem...
Michalis D. Galanis, Grigoris Dimitroulakos, Const...
MIDDLEWARE
2001
Springer
15 years 1 months ago
Thread Transparency in Information Flow Middleware
Abstract. Existing middleware is based on control-flow centric interaction models such as remote method invocations, poorly matching the structure of applications that process con...
Rainer Koster, Andrew P. Black, Jie Huang, Jonatha...
VIS
2009
IEEE
326views Visualization» more  VIS 2009»
15 years 10 months ago
Continuous Parallel Coordinates
Typical scientific data is represented on a grid with appropriate interpolation or approximation schemes, defined on a continuous domain. The visualization of such data in parallel...
Julian Heinrich, Daniel Weiskopf
IPPS
2005
IEEE
15 years 3 months ago
Practical Performance Model for Optimizing Dynamic Load Balancing of Adaptive Applications
Optimizing the performance of dynamic load balancing toolkits and applications requires the adjustment of several runtime parameters; however, determining sufficiently good value...
Kevin Barker, Nikos Chrisochoides