This paper presents a model for instruction-level distributed computing that allows the implementation of scalable chip multiprocessors. Based on explicit microthreading it serves ...
A design flow for processor platforms with on-chip coarse-grain reconfigurable logic is presented. The reconfigurable logic is realized by a 2-Dimensional Array of Processing Elem...
Michalis D. Galanis, Grigoris Dimitroulakos, Const...
Abstract. Existing middleware is based on control-flow centric interaction models such as remote method invocations, poorly matching the structure of applications that process con...
Rainer Koster, Andrew P. Black, Jie Huang, Jonatha...
Typical scientific data is represented on a grid with appropriate interpolation or approximation schemes, defined on a continuous domain. The visualization of such data in parallel...
Optimizing the performance of dynamic load balancing toolkits and applications requires the adjustment of several runtime parameters; however, determining sufficiently good value...