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DAC
1999
ACM
16 years 25 days ago
A Low Power Hardware/Software Partitioning Approach for Core-Based Embedded Systems
We present a novel approach that minimizes the power consumption of embedded core-based systems through hardware/software partitioning. Our approach is based on the idea of mapping...
Jörg Henkel
CODES
2008
IEEE
15 years 6 months ago
Cache-aware optimization of BAN applications
Body-area sensor network or BAN-based health monitoring is increasingly becoming a popular alternative to traditional wired bio-monitoring techniques. However, most biomonitoring ...
Yun Liang, Lei Ju, Samarjit Chakraborty, Tulika Mi...
DAC
2004
ACM
16 years 25 days ago
High level cache simulation for heterogeneous multiprocessors
As multiprocessor systems-on-chip become a reality, performance modeling becomes a challenge. To quickly evaluate many architectures, some type of high-level simulation is require...
Joshua J. Pieper, Alain Mellan, JoAnn M. Paul, Don...
WSC
1997
15 years 1 months ago
Efficient Instruction Cache Simulation and Execution Profiling with a Threaded-Code Interpreter
We present an extension to an existing SPARC V8 instruction set simulator, SimICS, to support accurate profiling of branches and instruction cache misses. SimICS had previously su...
Peter S. Magnusson
SODA
2004
ACM
83views Algorithms» more  SODA 2004»
15 years 1 months ago
Caching queues in memory buffers
Motivated by the need for maintaining multiple, large queues of data in modern high-performance systems, we study the problem of caching queues in memory under the following simpl...
Rajeev Motwani, Dilys Thomas