433 search results - page 38 / 87 » Analytical cache models with applications to cache partition... |
ISCA
1999
IEEE
15 years 4 months ago
1999
IEEE
Providing adequate data bandwidth is extremely important for a wide-issue superscalar processor to achieve its full performance potential. Adding a large number of ports to a data...
147
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CAV
1998
Springer
15 years 4 months ago
1998
Springer
As a pedagogical exercise in ACL2, we formalize and prove the correctness of a write invalidate cache scheme. In our formalization, an arbitrary number of processors, each with its...
CITA
2005
IEEE
15 years 5 months ago
2005
IEEE
- We present an architecture for data streams based on structures typically found in web cache hierarchies. The main idea is to build a meta level analyser from a number of levels ...
136
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SIGMETRICS
1996
ACM
15 years 4 months ago
1996
ACM
This paper describes Embra, a simulator for the processors, caches, and memory systems of uniprocessors and cache-coherent multiprocessors. When running as part of the SimOS simul...
CASES
2001
ACM
15 years 3 months ago
2001
ACM
Today's digital signal processors (DSPs), unlike general-purpose processors, use a non-uniform addressing model in which the primary components of the memory system--the DRAM...