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AINA
2007
IEEE
15 years 6 months ago
Synthetic Trace-Driven Simulation of Cache Memory
The widening gap between CPU and memory speed has made caches an integral feature of modern highperformance processors. The high degree of configurability of cache memory can requ...
Rahman Hassan, Antony Harris, Nigel P. Topham, Ari...
IPPS
2002
IEEE
15 years 4 months ago
Memory-Intensive Benchmarks: IRAM vs. Cache-Based Machines
The increasing gap between processor and memory performance has led to new architectural models for memory-intensive applications. In this paper, we use a set of memory-intensive ...
Brian R. Gaeke, Parry Husbands, Xiaoye S. Li, Leon...
TC
2011
14 years 6 months ago
Software-Based Cache Coherence with Hardware-Assisted Selective Self-Invalidations Using Bloom Filters
— Implementing shared memory consistency models on top of hardware caches gives rise to the well-known cache coherence problem. The standard solution involves implementing cohere...
Thomas J. Ashby, Pedro Diaz, Marcelo Cintra
ISLPED
1997
ACM
99views Hardware» more  ISLPED 1997»
15 years 4 months ago
Low power data processing by elimination of redundant computations
We suggest a new technique to reduce energy consumption in the processor datapath without sacrificing performance by exploiting operand value locality at run time. Data locality is...
Mir Azam, Paul D. Franzon, Wentai Liu
SPAA
2004
ACM
15 years 5 months ago
Online algorithms for prefetching and caching on parallel disks
Parallel disks provide a cost effective way of speeding up I/Os in applications that work with large amounts of data. The main challenge is to achieve as much parallelism as poss...
Rahul Shah, Peter J. Varman, Jeffrey Scott Vitter