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PARELEC
2006
IEEE
15 years 5 months ago
Hierarchical Partitioning for Piecewise Linear Algorithms
processor arrays can be used as accelerators for a plenty of data flow-dominant applications. The explosive growth in research and development of massively parallel processor arr...
Hritam Dutta, Frank Hannig, Jürgen Teich
SIGMOD
2001
ACM
118views Database» more  SIGMOD 2001»
15 years 12 months ago
Proxy-Server Architectures for OLAP
Data warehouses have been successfully employed for assisting decision making by offering a global view of the enterprise data and providing mechanisms for On-Line Analytical proc...
Panos Kalnis, Dimitris Papadias
CC
2010
Springer
190views System Software» more  CC 2010»
15 years 6 months ago
Is Reuse Distance Applicable to Data Locality Analysis on Chip Multiprocessors?
On Chip Multiprocessors (CMP), it is common that multiple cores share certain levels of cache. The sharing increases the contention in cache and memory-to-chip bandwidth, further h...
Yunlian Jiang, Eddy Z. Zhang, Kai Tian, Xipeng She...
MICRO
2009
IEEE
133views Hardware» more  MICRO 2009»
15 years 6 months ago
A tagless coherence directory
A key challenge in architecting a CMP with many cores is maintaining cache coherence in an efficient manner. Directory-based protocols avoid the bandwidth overhead of snoop-based ...
Jason Zebchuk, Vijayalakshmi Srinivasan, Moinuddin...
MICRO
2010
IEEE
215views Hardware» more  MICRO 2010»
14 years 10 months ago
A Task-Centric Memory Model for Scalable Accelerator Architectures
This paper presents a task-centric memory model for 1000-core compute accelerators. Visual computing applications are emerging as an important class of workloads that can exploit ...
John H. Kelm, Daniel R. Johnson, Steven S. Lumetta...