Clock distribution is one of the key limiting factors in any high speed, sub-100nm VLSI design. Unwanted clock skews, caused by variation effects like manufacturing variations, po...
In this paper, we address the interconnect-driven floorplanning problem that integrates OPC-friendly bus assignment with floorplanning. Buses consist of a number of horizontal/v...
Hua Xiang, Liang Deng, Li-Da Huang, Martin D. F. W...
—Handheld devices have become sufficiently powerful that it is easy to create, disseminate, and access digital content (e.g., photos, videos) using them. The volume of such cont...
The high demand for large scale storage capacity calls for the availability of massive storage solutions with high performance interconnects. Although cluster file systems are rap...
Online auction sites have unique workloads and user behavior characteristics that do not exist in other e-commerce sites. Earlier studies by the authors identified i) significan...