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GLVLSI
2009
IEEE
189views VLSI» more  GLVLSI 2009»
15 years 4 months ago
High-performance, cost-effective heterogeneous 3D FPGA architectures
In this paper, we propose novel architectural and design techniques for three-dimensional field-programmable gate arrays (3D FPGAs) with Through-Silicon Vias (TSVs). We develop a...
Roto Le, Sherief Reda, R. Iris Bahar
IEEEPACT
2007
IEEE
15 years 4 months ago
Performance Portable Optimizations for Loops Containing Communication Operations
Effective use of communication networks is critical to the performance and scalability of parallel applications. Partitioned Global Address Space languages like UPC bring the pro...
Costin Iancu, Wei Chen, Katherine A. Yelick
RTSS
2005
IEEE
15 years 3 months ago
ParaScale: Exploiting Parametric Timing Analysis for Real-Time Schedulers and Dynamic Voltage Scaling
Static timing analysis safely bounds worst-case execution times to determine if tasks can meet their deadlines in hard real-time systems. However, conventional timing analysis req...
Sibin Mohan, Frank Mueller, William Hawkins, Micha...
LPAR
2004
Springer
15 years 3 months ago
Abstraction-Carrying Code
ion-Carrying Code Elvira Albert1 , Germ´an Puebla2 , and Manuel Hermenegildo2,3 1 DSIP, Universidad Complutense Madrid 2 Facultad de Inform´atica, Technical University of Madrid ...
Elvira Albert, Germán Puebla, Manuel V. Her...
PODS
2010
ACM
306views Database» more  PODS 2010»
15 years 2 months ago
Optimizing linear counting queries under differential privacy
Differential privacy is a robust privacy standard that has been successfully applied to a range of data analysis tasks. But despite much recent work, optimal strategies for answe...
Chao Li, Michael Hay, Vibhor Rastogi, Gerome Mikla...