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» Analyzing Failure Recovery to Improve Planner Design
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ATS
2005
IEEE
104views Hardware» more  ATS 2005»
15 years 3 months ago
Leakage Current Based Stabilization Scheme for Robust Sense-Amplifier Design for Yield Enhancement in Nano-scale SRAM
In this paper, we develop a method to analyze the probability of access failure in SRAM array (due to random Vt variation in transistors) by jointly considering variations in cell...
Saibal Mukhopadhyay, Arijit Raychowdhury, Hamid Ma...
DATE
2005
IEEE
154views Hardware» more  DATE 2005»
15 years 3 months ago
Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit
We present a complete top-down design of a low-power multi-channel clock recovery circuit based on gated current-controlled oscillators. The flow includes several tools and method...
Paul Muller, Armin Tajalli, Seyed Mojtaba Atarodi,...
JSS
2007
78views more  JSS 2007»
14 years 9 months ago
Understanding failure response in service discovery systems
Service discovery systems enable distributed components to find each other without prior arrangement, to express capabilities and needs, to aggregate into useful compositions, an...
Christopher Dabrowski, Kevin Mills, Stephen Quirol...
HPDC
2012
IEEE
12 years 12 months ago
Understanding the effects and implications of compute node related failures in hadoop
Hadoop has become a critical component in today’s cloud environment. Ensuring good performance for Hadoop is paramount for the wide-range of applications built on top of it. In ...
Florin Dinu, T. S. Eugene Ng
NOSSDAV
2005
Springer
15 years 3 months ago
1-800-OVERLAYS: using overlay networks to improve VoIP quality
The cost savings and novel features associated with Voice over IP (VoIP) are driving its adoption by service providers. Such a transition however can successfully happen only if t...
Yair Amir, Claudiu Danilov, Stuart Goose, David He...