23 search results - page 4 / 5 » Analyzing timing uncertainty in mesh-based clock architectur... |
ICASSP
2011
IEEE
12 years 10 months ago
2011
IEEE
In this paper, based on the proposed parallelization scheme of binary arithmetic decoding, a parallel AVC/H.264 context-based adaptive binary arithmetic coding (CABAC) decoder wit...
QEST
2010
IEEE
13 years 4 months ago
2010
IEEE
Traditional architecture design approaches hide hardware uncertainties from the software stack through overdesign, which is often expensive in terms of power consumption. The recen...
HIPEAC
2009
Springer
14 years 1 months ago
2009
Springer
In this article, we present a parallel implementation of a 1024 point Fast Fourier Transform (FFT) operating with a subthreshold supply voltage, which is below the voltage that tur...
DAC
1997
ACM
13 years 10 months ago
1997
ACM
Cr, As the complexity of high-performance microprocessor increases, functional verification becomes more and more difficult and RTL simulation emerges as the bottleneck of the des...
FPGA
2004
ACM
13 years 11 months ago
2004
ACM
The speedup over a microprocessor that can be achieved by implementing some programs on an FPGA has been extensively reported. This paper presents an analysis, both quantitative a...