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ICCAD
2004
IEEE
127views Hardware» more  ICCAD 2004»
15 years 11 months ago
A yield improvement methodology using pre- and post-silicon statistical clock scheduling
— In deep sub-micron technologies, process variations can cause significant path delay and clock skew uncertainties thereby lead to timing failure and yield loss. In this paper,...
Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Pin...
FPGA
2010
ACM
243views FPGA» more  FPGA 2010»
15 years 11 months ago
Bit-level optimization for high-level synthesis and FPGA-based acceleration
d hardware design from behavior-level abstraction has drawn wide interest in FPGA-based acceleration and configurable computing research field. However, for many high-level progra...
Jiyu Zhang, Zhiru Zhang, Sheng Zhou, Mingxing Tan,...
CVPR
2010
IEEE
1192views Computer Vision» more  CVPR 2010»
15 years 11 months ago
RASL: Robust Alignment by Sparse and Low-rank Decomposition for Linearly Correlated Images
This paper studies the problem of simultaneously aligning a batch of linearly correlated images despite gross corruption (such as occlusion). Our method seeks an optimal set of im...
Yigang Peng, Arvind Balasubramanian, John Wright, ...
112
Voted
CVPR
2010
IEEE
15 years 10 months ago
Efficiently Selecting Regions for Scene Understanding
Recent advances in scene understanding and related tasks have highlighted the importance of using regions to reason about high-level scene structure. Typically, the regions are ...
M. Pawan Kumar, Daphne Koller
WWW
2010
ACM
15 years 9 months ago
Debugging standard document formats
We present a tool for helping XML schema designers to obtain a high quality level for their specifications. The tool allows one to analyze relations between classes of XML docume...
Nabil Layaïda, Pierre Genevès
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