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PEPM
1998
ACM
15 years 6 months ago
Type-Directed Partial Evaluation
Abstract. We use a code generator--type-directed partial evaluation-to verify conversions between isomorphic types, or more precisely to verify that a composite function is the ide...
Olivier Danvy
74
Voted
ISCA
1997
IEEE
96views Hardware» more  ISCA 1997»
15 years 6 months ago
DataScalar Architectures
DataScalar architectures improve memory system performance by running computation redundantly across multiple processors, which are each tightly coupled with an associated memory....
Doug Burger, Stefanos Kaxiras, James R. Goodman
DAC
1997
ACM
15 years 6 months ago
Analysis and Evaluation of Address Arithmetic Capabilities in Custom DSP Architectures
—Many application-specific architectures provide indirect addressing modes with auto-increment/decrement arithmetic. Since these architectures generally do not feature an indexe...
Ashok Sudarsanam, Stan Y. Liao, Srinivas Devadas
APSEC
1996
IEEE
15 years 6 months ago
M-base : An Application Development Environment for End-user Computing based on Message Flow
Explosive increase in end-user computing on distributed systems requires that end-users develop application software by themselves. One solution is given as aformula of "adom...
Takeshi Chusho, Yuji Konishi, Masao Yoshioka
FPGA
1997
ACM
127views FPGA» more  FPGA 1997»
15 years 6 months ago
General Modeling and Technology-Mapping Technique for LUT-Based FPGAs
We present a general approach to the FPGA technology mapping problem that applies to any logic block composed of lookup tables LUTs and can yield optimal solutions. The connecti...
Amit Chowdhary, John P. Hayes
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