1775 search results - page 83 / 355 » Antichains on Three Levels |
ICNP
1999
IEEE
15 years 2 months ago
1999
IEEE
For wireless channels, interference mitigation techniques are typically applied at the packet transmission level. In this paper, we present the Havana Framework for supporting int...
IPPS
1998
IEEE
15 years 2 months ago
1998
IEEE
List-based priority schedulers have long been one of the dominant classes of static scheduling algorithms. Such heuristics have been predominantly based around the "critical ...
HPCA
1997
IEEE
15 years 2 months ago
1997
IEEE
Processors with write-through caches typically require a write buffer to hide the write latency to the next level of memory hierarchy and to reduce write traffic. A write buffer ...
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CONPAR
1994
15 years 2 months ago
1994
The Rewrite Rule Machine (RRM) is a massively parallel MIMD/SIMD computer designed with the explicit purpose of supporting veryhigh-level parallel programming with rewrite rules. T...
CIVR
2004
Springer
15 years 1 months ago
2004
Springer
We address the problem of classifying scenes from feature films into semantic categories and propose a robust framework for this problem. We propose that the Finite State Machines ...