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HPCN
1998
Springer
15 years 10 months ago
The GRED Graphical Editor for the GRADE Parallel Program Development Environment
In this paper, we describe a graphical editor GRED as part of the integrated programming environment GRADE that is intended to support designing, debugging and performance tuning o...
Péter Kacsuk, Gábor Dózsa, Ti...
ICASSP
2011
IEEE
14 years 10 months ago
A methodology based on Transportation problem modeling for designing parallel interleaver architectures
For high-data-rate applications, turbo-like iterative decoders are implemented with parallel hardware architecture. However, to achieve high throughput, concurrent accesses to each...
Awais Sani, Philippe Coussy, Cyrille Chavet, Eric ...
164
Voted
ARCS
2004
Springer
15 years 11 months ago
A Comparison of Parallel Programming Models of Network Processors
: Today’s network processor utilize parallel processing in order to cope with the traffic growth and wire-speed of current and future network technologies. In this paper, we stu...
Carsten Albrecht, Rainer Hagenau, Erik Maehle, And...
FCCM
2006
IEEE
108views VLSI» more  FCCM 2006»
16 years 12 days ago
A Reconfigurable Distributed Computing Fabric Exploiting Multilevel Parallelism
This paper presents a novel reconfigurable data flow processing architecture that promises high performance by explicitly targeting both fine- and course-grained parallelism. This...
Charles L. Cathey, Jason D. Bakos, Duncan A. Buell
ISCAS
2005
IEEE
124views Hardware» more  ISCAS 2005»
15 years 12 months ago
Parallel FFT computation with a CDMA-based network-on-chip
— Fast Fourier transform (FFT) algorithms are used in a wide variety of digital signal processing applications and many of these require high-performance parallel implementations...
Daewook Kim, Manho Kim, Gerald E. Sobelman