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VLSID
2001
IEEE
164views VLSI» more  VLSID 2001»
15 years 10 months ago
An Efficient Parallel Transparent Bist Method For Multiple Embedded Memory Buffers
In this paper, we propose a new transparent built-in self-test ( TBIST ) method to test multiple embedded memory arrays with various sizes in parallel. First, a new transparent tes...
Der-Cheng Huang, Wen-Ben Jone, Sunil R. Das
ASAP
2004
IEEE
101views Hardware» more  ASAP 2004»
15 years 1 months ago
Register Organization for Enhanced On-Chip Parallelism
Large register file with multiple ports is a critical component of a high-performance processor. A large number of registers are necessary for processing a larger number of in-fli...
Rama Sangireddy
JPDC
2006
85views more  JPDC 2006»
14 years 9 months ago
Provable algorithms for parallel generalized sweep scheduling
We present provably efficient parallel algorithms for sweep scheduling, which is a commonly used technique in Radiation Transport problems, and involves inverting an operator by i...
V. S. Anil Kumar, Madhav V. Marathe, Srinivasan Pa...
PATMOS
2000
Springer
15 years 1 months ago
Data-Reuse and Parallel Embedded Architectures for Low-Power, Real-Time Multimedia Applications
Exploitation of data re-use in combination with the use of custom memory hierarchy that exploits the temporal locality of data accesses may introduce significant power savings, esp...
Dimitrios Soudris, Nikolaos D. Zervas, Antonios Ar...
ICS
2001
Tsinghua U.
15 years 2 months ago
Cache performance for multimedia applications
The caching behavior of multimedia applications has been described as having high instruction reference locality within small loops, very large working sets, and poor data cache p...
Nathan T. Slingerland, Alan Jay Smith