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MICRO
2010
IEEE
156views Hardware» more  MICRO 2010»
15 years 22 days ago
Explicit Communication and Synchronization in SARC
SARC merges cache controller and network interface functions by relying on a single hardware primitive: each access checks the tag and the state of the addressed line for possible...
Manolis Katevenis, Vassilis Papaefstathiou, Stamat...
ICRA
2010
IEEE
178views Robotics» more  ICRA 2010»
15 years 7 days ago
Biomimetic optic flow sensing applied to a lunar landing scenario
Autonomous landing on unknown extraterrestrial bodies requires fast, noise-resistant motion processing to elicit appropriate steering commands. Flying insects excellently master vi...
Florent Valette, Franck Ruffier, Stéphane V...
HPCA
2009
IEEE
16 years 2 months ago
Prediction router: Yet another low latency on-chip router architecture
Network-on-Chips (NoCs) are quite latency sensitive, since their communication latency strongly affects the application performance on recent many-core architectures. To reduce th...
Hiroki Matsutani, Michihiro Koibuchi, Hideharu Ama...
124
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HPCA
2003
IEEE
16 years 2 months ago
Memory System Behavior of Java-Based Middleware
Java-based middleware, and application servers in particular, are rapidly gaining importance as a new class of workload for commercial multiprocessor servers. SPEC has recognized ...
Martin Karlsson, Kevin E. Moore, Erik Hagersten, D...
SC
2009
ACM
15 years 9 months ago
OddCI: on-demand distributed computing infrastructure
The availability of large quantities of processors is a crucial enabler of many-task computing. Voluntary computing systems have proven that it is possible to build computing plat...
Rostand Costa, Francisco V. Brasileiro, Guido Lemo...