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SIGPLAN
2008
15 years 1 months ago
A parallel dynamic compiler for CIL bytecode
Multi-core technology is being employed in most recent high-performance architectures. Such architectures need specifically designed multi-threaded software to exploit all the pot...
Simone Campanoni, Giovanni Agosta, Stefano Crespi-...
RTAS
2005
IEEE
15 years 7 months ago
Hybrid Supervisory Utilization Control of Real-Time Systems
Feedback control real-time scheduling (FCS) aims at satisfying performance specifications of real-time systems based on adaptive resource management. Existing FCS algorithms often...
Xenofon D. Koutsoukos, Radhika Tekumalla, Balachan...
ISCA
1998
IEEE
119views Hardware» more  ISCA 1998»
15 years 5 months ago
Using Prediction to Accelerate Coherence Protocols
Most large shared-memory multiprocessors use directory protocols to keep per-processor caches coherent. Some memory references in such systems, however, suffer long latencies for ...
Shubhendu S. Mukherjee, Mark D. Hill
CTRSA
2006
Springer
146views Cryptology» more  CTRSA 2006»
15 years 5 months ago
Cache Attacks and Countermeasures: The Case of AES
We describe several software side-channel attacks based on inter-process leakage through the state of the CPU's memory cache. This leakage reveals memory access patterns, whic...
Dag Arne Osvik, Adi Shamir, Eran Tromer
105
Voted
FPL
2006
Springer
111views Hardware» more  FPL 2006»
15 years 5 months ago
A Simulation Platform for Reconfigurable Computing Research
In this paper, we present a full-system reconfigurable computing simulation platform intended to promote innovative new research in reconfigurable computing. Currently, reconfigur...
Wenyin Fu, Katherine Compton