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ESTIMEDIA
2004
Springer
15 years 7 months ago
A queuing-theoretic performance model for context-flow system-on-chip platforms
Abstract—Few analytical performance models that relate performance figure of merit to architectural design decisions are reported in recent studies of network-on-chip, which pre...
Rami Beidas, Jianwen Zhu
ICCAD
1997
IEEE
162views Hardware» more  ICCAD 1997»
15 years 5 months ago
Application-driven synthesis of core-based systems
We developed a new hierarchical modular approach for synthesis of area-minimal core-based data-intensive systems. The optimization approach employs a novel global least-constraini...
Darko Kirovski, Chunho Lee, Miodrag Potkonjak, Wil...
ICIP
1998
IEEE
16 years 3 months ago
Hardware Architecture for Optical Flow Estimation in Real Time
Optical flow estimation from image sequences has been for several years a mathematical process carried out by general purpose processors in no real time. In this work a specific a...
Aitzol Zuloaga, José Luis Martín, Jo...
ICIP
1995
IEEE
16 years 3 months ago
Parallel programmable video co-processor design
Modern video applications call for computationally intensive data processing at very high data rate. In order to meet the high-performance/low-cost constraints, the stateof-the-ar...
An-Yeu Wu, K. J. Ray Liu, Arun Raghupathy, Shang-C...
CASES
2003
ACM
15 years 6 months ago
Lattice-based memory allocation
—We investigate the problem of memory reuse in order to reduce the memory needed to store an array variable. We develop techniques that can lead to smaller memory requirements in...
Alain Darte, Robert Schreiber, Gilles Villard