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PDP
2010
IEEE
15 years 4 months ago
Energy-Efficient Hardware Prefetching for CMPs Using Heterogeneous Interconnects
In the last years high performance processor designs have evolved toward Chip-Multiprocessor (CMP) architectures that implement multiple processing cores on a single die. As the nu...
Antonio Flores, Juan L. Aragón, Manuel E. A...
DATE
2006
IEEE
171views Hardware» more  DATE 2006»
15 years 5 months ago
Dynamic bit-width adaptation in DCT: image quality versus computation energy trade-off
We present a dynamic bit-width adaptation scheme in DCT applications for efficient trade-off between image quality and computation energy. Based on sensitivity differences of 64 ...
Jongsun Park, Jung Hwan Choi, Kaushik Roy
DAC
2002
ACM
16 years 21 days ago
An energy saving strategy based on adaptive loop parallelization
In this paper, we evaluate an adaptive loop parallelization strategy (i.e., a strategy that allows each loop nest to execute using different number of processors if doing so is be...
Ismail Kadayif, Mahmut T. Kandemir, Mustafa Karak&...
VLSISP
2010
148views more  VLSISP 2010»
14 years 10 months ago
Energy-efficient Hardware Architecture and VLSI Implementation of a Polyphase Channelizer with Applications to Subband Adaptive
Abstract Polyphase channelizer is an important component of subband adaptive filtering systems. This paper presents an energy-efficient hardware architecture and VLSI implementatio...
Yongtao Wang, Hamid Mahmoodi, Lih-Yih Chiou, Hunso...
DCOSS
2005
Springer
15 years 5 months ago
Design of Adaptive Overlays for Multi-scale Communication in Sensor Networks
In wireless sensor networks, energy and communication bandwidth are precious resources. Traditionally, layering has been used as a design principle for network stacks; hence routin...
Santashil PalChaudhuri, Rajnish Kumar, Richard G. ...