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ETS
2007
IEEE
128views Hardware» more  ETS 2007»
15 years 1 months ago
Selecting Power-Optimal SBST Routines for On-Line Processor Testing
Software-Based Self-Test (SBST) has emerged as an effective strategy for on-line testing of processors integrated in non-safety critical embedded system applications. Among the mo...
Andreas Merentitis, Nektarios Kranitis, Antonis M....
VLSID
2002
IEEE
123views VLSI» more  VLSID 2002»
16 years 6 days ago
Compiler-Directed Array Interleaving for Reducing Energy in Multi-Bank Memories
With the increased use of embedded/portable devices such as smart cellular phones, pagers, PDAs, hand-held computers, and CD players, improving energy efficiency is becoming a cri...
Victor Delaluz, Mahmut T. Kandemir, Narayanan Vija...
ISLPED
2009
ACM
168views Hardware» more  ISLPED 2009»
15 years 6 months ago
A 60fps 496mW multi-object recognition processor with workload-aware dynamic power management
An energy efficient object recognition processor is proposed for real-time visual applications. Its energy efficiency is improved by lowering average power consumption while susta...
Joo-Young Kim, Seungjin Lee, Jinwook Oh, Minsu Kim...
VLSID
2003
IEEE
134views VLSI» more  VLSID 2003»
16 years 6 days ago
A Framework for Energy and Transient Power Reduction during Behavioral Synthesis
Abstract-- In battery driven portable applications, the minimization of energy, average power, peak power, and peak power differential are equally important to improve reliability ...
Saraju P. Mohanty, N. Ranganathan
AINA
2006
IEEE
15 years 3 months ago
Constrained Flooding: A Robust and Efficient Routing Framework for Wireless Sensor Networks
Flooding protocols for wireless networks in general have been shown to be very inefficient and therefore are mainly used in network initialization or route discovery and maintenan...
Ying Zhang, Markus P. J. Fromherz