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» Application mapping for chip multiprocessors
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EDCC
2008
Springer
14 years 11 months ago
A Transient-Resilient System-on-a-Chip Architecture with Support for On-Chip and Off-Chip TMR
The ongoing technological advances in the semiconductor industry make Multi-Processor System-on-a-Chips (MPSoCs) more attractive, because uniprocessor solutions do not scale satis...
Roman Obermaisser, Hubert Kraut, Christian El Sall...
HPCA
2006
IEEE
15 years 10 months ago
Dynamic power-performance adaptation of parallel computation on chip multiprocessors
Previous proposals for power-aware thread-level parallelism on chip multiprocessors (CMPs) mostly focus on multiprogrammed workloads. Nonetheless, parallel computation of a single...
Jian Li, José F. Martínez
HPCA
2011
IEEE
14 years 1 months ago
Shared last-level TLBs for chip multiprocessors
Translation Lookaside Buffers (TLBs) are critical to processor performance. Much past research has addressed uniprocessor TLBs, lowering access times and miss rates. However, as c...
Abhishek Bhattacharjee, Daniel Lustig, Margaret Ma...
CODES
2004
IEEE
15 years 1 months ago
Benchmark-based design strategies for single chip heterogeneous multiprocessors
Single chip heterogeneous multiprocessors are arising to meet the computational demands of portable and handheld devices. These computing systems are not fully custom designs trad...
JoAnn M. Paul, Donald E. Thomas, Alex Bobrek
ICPP
2003
IEEE
15 years 2 months ago
Performance and Power Impact of Issue-width in Chip-Multiprocessor Cores
In chip-multiprocessors (CMPs), the number of cores and the issue width of each core presents an important design trade-off to balance the amount of TLP and ILP between multi-thre...
Magnus Ekman, Per Stenström