Sciweavers

422 search results - page 20 / 85
» Application mapping for chip multiprocessors
Sort
View
DATE
2007
IEEE
105views Hardware» more  DATE 2007»
15 years 4 months ago
Understanding voltage variations in chip multiprocessors using a distributed power-delivery network
— Recent efforts to address microprocessor power dissipation through aggressive supply voltage scaling and power management require that designers be increasingly cognizant of po...
Meeta Sharma Gupta, Jarod L. Oatley, Russ Joseph, ...
DATE
2007
IEEE
114views Hardware» more  DATE 2007»
15 years 4 months ago
Mapping the physical layer of radio standards to multiprocessor architectures
We are concerned with the software implementation of baseband processing for the physical layer of radio standards (“Software Defined Radio - SDR”). Given the constraints for ...
Cyprian Grassmann, Mathias Richter, Mirko Sauerman...
JSA
2008
91views more  JSA 2008»
14 years 9 months ago
Using supplier locality in power-aware interconnects and caches in chip multiprocessors
Conventional snoopy-based chip multiprocessors take an aggressive approach broadcasting snoop requests to all nodes. In addition each node checks all received requests. This appro...
Ehsan Atoofian, Amirali Baniasadi
86
Voted
FPL
2007
Springer
146views Hardware» more  FPL 2007»
15 years 3 months ago
Efficient External Memory Interface for Multi-processor Platforms Realized on FPGA Chips
The complexity of today’s embedded applications requires modern high-performance embedded System-on-Chip (SoC) platforms to be multiprocessor architectures. Advances in FPGA tec...
Hristo Nikolov, Todor Stefanov, Ed F. Deprettere
92
Voted
ISCA
2003
IEEE
136views Hardware» more  ISCA 2003»
15 years 2 months ago
Transient-Fault Recovery for Chip Multiprocessors
To address the increasing susceptibility of commodity chip multiprocessors (CMPs) to transient faults, we propose Chiplevel Redundantly Threaded multiprocessor with Recovery (CRTR...
Mohamed A. Gomaa, Chad Scarbrough, Irith Pomeranz,...