422 search results - page 27 / 85 » Application mapping for chip multiprocessors |
DATE
2003
IEEE
15 years 3 months ago
2003
IEEE
In system-level platform-based embedded systems design, the mapping model is a crucial link between the application model and the architecture model. All three models must match w...
IWSOC
2003
IEEE
15 years 2 months ago
2003
IEEE
This paper addresses some fundamental issues relating to the design of systems on chip that utilize optical interconnects. We present an information theoretical model for assessin...
83
Voted
IEEEPACT
2009
IEEE
15 years 4 months ago
2009
IEEE
— This research demonstrates that coming support for hardware transactional memory can be leveraged to significantly reduce the cost of implementing true speculative multithread...
CF
2005
ACM
14 years 11 months ago
2005
ACM
Thread-level speculative execution is a technique that makes it possible for a wider range of single-threaded applications to make use of the processing resources in a chip multip...
EUROPAR
2010
Springer
14 years 10 months ago
2010
Springer
Abstract. Performance of the on-chip cache is critical for processor. The multithread program model usually employed by on-chip many-core architectures may have effects on cache ac...