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» Application mapping for chip multiprocessors
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CODES
2007
IEEE
14 years 11 months ago
Incremental run-time application mapping for homogeneous NoCs with multiple voltage levels
In this paper, we propose an efficient technique for run-time application mapping onto Network-on-Chip (NoC) platforms with multiple voltage levels. Our technique consists of a re...
Chen-Ling Chou, Radu Marculescu
ISSS
2002
IEEE
126views Hardware» more  ISSS 2002»
15 years 2 months ago
Unifying Memory and Processor Wrapper Architecture in Multiprocessor SoC Design
In this paper, we present a new methodology for application specific multiprocessor system-on-chip design. This approach facilitates the integration of existing components with th...
Ahmed Amine Jerraya, Damien Lyonnard, Samy Meftali...
SAMOS
2007
Springer
15 years 3 months ago
Mapping and Performance Evaluation for Heterogeneous MP-SoCs Via Packing
The computational demand of signal processing algorithms is rising continuously. Heterogeneous embedded multiprocessor systems-on-chips are one solution to tackle this demand. But ...
Bastian Ristau, Gerhard Fettweis
FPL
2009
Springer
105views Hardware» more  FPL 2009»
15 years 1 months ago
Run-time resource management in fault-tolerant network on reconfigurable chips
This paper investigates the challenges of run-time resource management in future coarse-grained network-onreconfigurable-chips (NoRCs). Run-time reconfiguration is a key feature e...
Mohammad Hosseinabady, José L. Nú&nt...
ICCD
2006
IEEE
128views Hardware» more  ICCD 2006»
15 years 6 months ago
Polaris: A System-Level Roadmap for On-Chip Interconnection Networks
Technology trends are driving parallel on-chip architectures in the form of multi-processor systems-on-a-chip (MPSoCs) and chip multi-processors (CMPs). In these systems the incre...
Vassos Soteriou, Noel Eisley, Hangsheng Wang, Bin ...